128 byte cache line memory controller for non-standard dimm architecture

A dual in-line memory module (DIMM) system, comprising

• a printed circuit board;
• a 144 bit system controller mounted on the printed circuit board;
• first and second 80 bit sockets mounted on the printed circuit board and connected to the 144 bit system controller;
• a first DIMM connected to the first 80 bit socket, the first DIMM being an 80 bit DIMM populated with 80 bits of DRAM chips;
• a second DIMM connected to the second 80 bit socket, the second DIMM being an 80 bit sized DIMM populated with 64 bits of DRAM chips and has 16 bits of DRAM chip space unpopulated;
• and
• a total processing capacity of the first and second DIMMs combined being 144 bits;
• wherein the 144 bit system controller communicates with the first and second 80 bit sockets and the first and second DIMMs by a 128 byte cache line.