US 2026/0101734 A1 · FULLY SELF-ALIGNED VIA (FSAV) ON SUBTRACTIVE METAL

Abstract

An integrated circuit (IC) is described. The IC includes a dielectric layer of a first dielectric material. The IC also includes a first metal layer in the dielectric layer. The first metal layer has a first adhesion layer on a backside surface, a second adhesion layer on a frontside surface of the first metal layer. Additionally, the first metal layer has dielectric alignment structures on the second adhesion layer of a second dielectric material different from the first dielectric material. The IC further includes a second metal layer landing on the second adhesion layer on the frontside surface of the first metal layer, between the dielectric alignment structures.

Claims20

Dependent claims

An integrated circuit (IC), comprising:

a dielectric layer of a first dielectric material;
a first metal layer in the dielectric layer and having a first adhesion layer on a backside surface, a second adhesion layer on a frontside surface of the first metal layer and dielectric alignment structures on the second adhesion layer of a second dielectric material different from the first dielectric material;
and
a second metal layer landing on the second adhesion layer on the frontside surface of the first metal layer, between the dielectric alignment structures.

1 more element

A method for forming a fully self-aligned via, comprising:

forming a multilayer stack including a first metal layer on a first adhesion layer, a second adhesion layer on the first metal layer, and a hardmask layer on the second adhesion layer;
performing subtractive metal patterning to form first metal interconnects having the first adhesion layer on a backside surface and the second adhesion layer on a frontside surface;
forming dielectric alignment structures on the second adhesion layer of the first metal interconnects;
etching a via opening through a first dielectric layer to expose the second adhesion layer between the dielectric alignment structures of a selected metal interconnect;
and
depositing a second metal layer in the via opening and on a surface of the first dielectric layer.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/908,516Filed 7 Oct 2024

Published

9 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 20/425
Characterised by their conductive parts: barrier, adhesion or liner layers
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Fully self-aligned via (fsav) on subtractive metal

Life of this patent

Fully self-aligned via (fsav) on subtractive metal

Life of this patent

Abstract

Claims20