US 2026/0101498 A1 · THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Abstract

A three-dimensional semiconductor device includes a stack of alternating memory cell layers and insulating layers over a substrate, and several bit lines formed on the substrate and separated from each other. The bit lines and the memory cell layers define an array of stacked memory cells that includes several memory cells. One of the memory cells includes a body, a gate structure and a conductive portion. The body that is on the substrate has a first surface and a second surface opposite the first surface. One side of the body is connected to one of the bit lines. The gate structure and the conductive portion are formed on the opposite first and second surfaces. The conductive portion is formed between adjacent memory cell layers and is in direct contact with the body.

Claims20

Dependent claims

A three-dimensional semiconductor device, comprising:

a plurality of memory cell layers and a plurality of insulating layers disposed in an alternating manner over a substrate;
a plurality of bit lines on the substrate and separated from each other, wherein the bit lines and the memory cell layers define an array of stacked memory cells comprising a plurality of memory cells, wherein each of the memory cells comprises:
a body on the substrate, wherein one side of the body is connected to one of the bit lines;
and
a gate structure and a conductive portion on a first surface and a second surface of the body,
wherein the conductive portion is between adjacent memory cell layers and in direct contact with the body.

3 more elements

Dependencies are inferred from the claim text.

Three-dimensional semiconductor device

Life of this patent

Three-dimensional semiconductor device

Life of this patent

Abstract

Claims20