US 2026/0096492 A1 · PROCESSES FOR MANUFACTURING WAFER-ON-WAFER DEVICES, AND SYSTEMS INCORPORATING SUCH DEVICES

Abstract

Described herein are various embodiments of wafer-on-wafer manufacturing processes and devices that can be produced during or as a result of such processes. In a wafer-on-wafer process, two or more wafers including semiconductor, conductive, and/or insulating material with circuit components formed thereon can be bonded and diced to yield assemblies each including multiple dies. In some implementations, one die can include one or more integrated passive devices (e.g., deep trench capacitors) and one die can include power delivery circuitry, such as power regulation circuitry (e.g., voltage regulation circuitry).

Claims20

Dependent claims

A device comprising:

an assembly including
a first die comprising a first integrated passive device (IPD),
at least one through-silicon via (TSV) extending through the first die from a first surface of the first die to a second surface of the first die, and
a second die comprising power delivery circuitry or a second IPD, wherein a surface of the second die is bonded to the first surface of the first die.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

19/342,383Filed 26 Sep 2025

Priority

30 Sep 2024

Published

2 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification2 codes

H10W 90/297
Configurations of stacked chips: characterised by the through-semiconductor vias [TSVs] in the stacked chips
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Processes for manufacturing wafer-on-wafer devices, and systems incorporating such devices

Life of this patent

Processes for manufacturing wafer-on-wafer devices, and systems incorporating such devices

Life of this patent

Abstract

Claims20