Asymmetric memory structures and methods of fabricating the same

A memory device, comprising:

• a channel layer;
• a gate structure on a backside of the channel layer, the gate structure having a top surface facing the channel layer;
• a drain structure on a frontside of the channel layer opposite to the backside, the drain structure having a first bottom surface facing the channel layer, the first bottom surface non-overlapping the top surface along a lateral direction, and the first bottom surface having a first width along the lateral direction;
• and
• a source structure on the frontside of the channel layer and adjacent to the drain structure, the source structure having a second bottom surface facing the channel layer, the second bottom surface overlapping the top surface along the lateral direction, and the second bottom surface having a second width along the lateral direction that is different from the first width.

A method of fabricating a memory cell, comprising:

• forming a first dielectric layer over a base structure;
• forming a word line structure in the first dielectric layer;
• forming a second dielectric layer over the word line structure;
• forming a back-side gate structure in the second dielectric layer, the back-side gate structure extending along a first lateral direction;
• forming a high-k gate dielectric layer over the back-side gate structure;
• forming a semiconductor layer over the high-k gate dielectric layer;
• and
• forming a source structure and a drain structure adjacent to the source structure along a second lateral direction perpendicular to the first lateral direction in a top view of the memory cell, the drain structure having a first bottom surface facing the semiconductor layer and the source structure having a second bottom surface facing the semiconductor layer, wherein the first bottom surface differs from the second bottom surface in area across the first lateral direction and the second lateral direction.