Stacked transistor memory cells and methods of forming the same

A method comprising:

• depositing a dielectric layer over a back side of a memory cell;
• depositing a hard mask over the dielectric layer;
• patterning a first opening in the hard mask, wherein the first opening extends over a first epitaxial source/drain region, a second epitaxial source/drain region, a first gate electrode, and a second gate electrode of the memory cell;
• depositing a photoresist over the hard mask and within the first opening;
• patterning a second opening in the photoresist, wherein the second opening extends across the first opening;
• depositing a mask material over the photoresist and within the second opening;
• removing the photoresist, wherein a region of mask material remains within the second opening;
• etching the dielectric layer using the hard mask and the region of mask material as an etch mask, wherein the etching forms recesses in the dielectric layer;
• and
• depositing conductive material in the recesses.

A memory device comprising:

• a first lower epitaxial source/drain region adjacent a second lower epitaxial source/drain region;
• a first lower gate electrode adjacent a first side of the first lower epitaxial source/drain region;
• a second lower gate electrode adjacent a second side of the second lower epitaxial source/drain region, wherein the second side is opposite the first side;
• a dielectric layer under the first lower epitaxial source/drain region, the second lower epitaxial source/drain region, the first lower gate electrode, and the second lower gate electrode;
• a first butted contact within the dielectric layer, wherein the first butted contact electrically connects the first lower epitaxial source/drain region to the second lower gate electrode;
• and
• a second butted contact within the dielectric layer, wherein the second butted contact electrically connects the second lower epitaxial source/drain region to the first lower gate electrode.