Dynamic random access memory (dram) with backend transistors

A device comprising:

• a dynamic random-access memory (DRAM) layer having a first side and a second side, the DRAM layer comprising:
• a plurality of capacitors;
• and
• an etch stop layer over the plurality of capacitors, the etch stop layer along the first side of the DRAM layer;
• and
• a transistor layer over the DRAM layer, the transistor layer having a first side and a second side, the first side of the transistor layer in direct contact with the etch stop layer of the DRAM layer.

A package comprising:

• a packaging component;
• and
• a dynamic random-access memory (DRAM) device coupled to the packaging component, the DRAM device comprising:
• a DRAM layer comprising a capacitor and a first interconnect structure;
• and
• a transistor layer over the DRAM layer, wherein the transistor layer comprises a transistor and a second interconnect structure, wherein the first interconnect structure tapers in a direction away from the transistor layer, and the second interconnect structure tapers in a direction away from the DRAM layer.