Semiconductor memory device

A semiconductor memory device comprising:

• a stack structure including word lines and interlayer insulating patterns alternately stacked on a semiconductor substrate, the word lines extending in a first direction parallel to a top surface of the semiconductor substrate;
• channel patterns intersecting the word lines and having a long axis in a second direction parallel to the top surface of the semiconductor substrate, the channel patterns spaced apart from each other on the semiconductor substrate in the first direction and in a third direction perpendicular to the top surface of the semiconductor substrate;
• a lower separation insulating layer on the semiconductor substrate on a first side of the stack structure;
• bit lines spaced apart from each other on the lower separation insulating layer in the first direction, each of the bit lines connected to first end portions of the channel patterns, which are spaced apart from each other in the third direction;
• and
• upper separation insulating patterns between the bit lines, respectively, and adjacent to each other in the first direction,
• wherein the lower separation insulating layer includes an insulating material having a lower dielectric constant than that of the upper separation insulating patterns.

A semiconductor memory device comprising:

• a stack structure including word lines and interlayer insulating patterns alternately stacked on a semiconductor substrate, the word lines extending in a first direction parallel to a top surface of the semiconductor substrate;
• channel patterns intersecting the word lines and having a long axis in a second direction parallel to the top surface of the semiconductor substrate, the channel patterns spaced apart from each other on the semiconductor substrate in the first direction and in a third direction perpendicular to the top surface of the semiconductor substrate;
• a lower separation insulating layer on the semiconductor substrate on a first side of the stack structure;
• bit lines spaced apart from each other in the first direction on the lower separation insulating layer, each of the bit lines connected to first end portions of the channel patterns, which are spaced apart from each other in the third direction;
• upper separation insulating patterns between the bit lines, respectively, and adjacent to each other in the first direction;
• first separation insulating patterns between the first end portions of the channel patterns, respectively, and spaced apart from each other in the first direction;
• second separation insulating patterns between second end portions opposite to the first end portions of the channel patterns, respectively, and spaced apart from each other in the first direction;
• and
• data storage elements between the interlayer insulating patterns, respectively, adjacent to each other in the third direction, and connected to the second end portions of the channel patterns.