US 2026/0089912 A1Published application

Semiconductor memory device

AssigneeKioxia Corporation

InventorsHidehiro SHIGA, Mutsumi OKAJIMA, Takeshi SUGIMOTO, Kenya TASHIRO

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Abstract

A semiconductor memory device comprises: first semiconductor layers stacked in a first direction; a via wiring electrically connected to the first semiconductor layers; memory portions electrically connected to the first semiconductor layers; first gate electrodes facing the first semiconductor layers; a first wiring and a second wiring provided on one side and the other side in the first direction with respect to the first semiconductor layers; a second semiconductor layer provided between the first semiconductor layers and the first wiring, and electrically connected to the via wiring; a first connecting electrode electrically connected to the first wiring and the second semiconductor layer; a third semiconductor layer provided between the first semiconductor layers and the second wiring, and electrically connected to the via wiring; and a second connecting electrode electrically connected to the second wiring and the third semiconductor layer.

Claims21

Dependent claims

A semiconductor memory device comprising:

a plurality of first semiconductor layers stacked in a first direction;
a via wiring which extends in the first direction, and is electrically connected to the plurality of first semiconductor layers;
a plurality of memory portions which are arranged in the first direction corresponding to the plurality of first semiconductor layers, and are electrically connected to the plurality of first semiconductor layers;
a plurality of first gate electrodes which are arranged in the first direction corresponding to the plurality of first semiconductor layers, and face the plurality of first semiconductor layers;
a first wiring provided on one side in the first direction with respect to the plurality of first semiconductor layers;
a second semiconductor layer which is provided between the plurality of first semiconductor layers and the first wiring, and is electrically connected to the via wiring;
a first connecting electrode which is provided between the plurality of memory portions and the first wiring, and is electrically connected to the first wiring and the second semiconductor layer;
a second gate electrode which is provided between the plurality of first gate electrodes and the first wiring, and faces the second semiconductor layer;
a second wiring provided on the other side in the first direction with respect to the plurality of first semiconductor layers;
a third semiconductor layer which is provided between the plurality of first semiconductor layers and the second wiring, and is electrically connected to the via wiring;
a second connecting electrode which is provided between the plurality of memory portions and the second wiring, and is electrically connected to the second wiring and the third semiconductor layer;
and
a third gate electrode which is provided between the plurality of first gate electrodes and the second wiring, and faces the third semiconductor layer.

10 more elements

A semiconductor memory device comprising:

a plurality of first semiconductor layers stacked in a first direction;
a via wiring which extends in the first direction, and is electrically connected to the plurality of first semiconductor layers;
a plurality of memory portions which are arranged in the first direction corresponding to the plurality of first semiconductor layers, and are electrically connected to the plurality of first semiconductor layers;
a plurality of first gate electrodes which are arranged in the first direction corresponding to the plurality of first semiconductor layers, and face the plurality of first semiconductor layers;
a first wiring which is provided on one side in the first direction with respect to the plurality of first semiconductor layers, and extends in a second direction intersecting the first direction;
a second semiconductor layer which is provided between the plurality of first semiconductor layers and the first wiring, and is electrically connected to the via wiring;
a first connecting electrode which is provided between the plurality of memory portions and the first wiring, and is electrically connected to the first wiring and the second semiconductor layer;
a second gate electrode which is provided between the plurality of first gate electrodes and the first wiring, and faces the second semiconductor layer;
a second wiring which extends in the first direction, and is arranged with the plurality of first semiconductor layers in the second direction;
a third semiconductor layer which is provided at a position overlapping the plurality of first semiconductor layers when viewed in the first direction, and is electrically connected to the via wiring;
a second connecting electrode which is provided at a position overlapping the plurality of memory portions when viewed in the first direction, and is electrically connected to the third semiconductor layer and the second wiring;
and
a third gate electrode which is provided at a position overlapping the plurality of first gate electrodes when viewed in the first direction, and faces the third semiconductor layer.

10 more elements

A semiconductor memory device comprising

a pair of memory structures and a first wiring separated from the pair of memory structures in a first direction, wherein
the pair of memory structures is arranged in a second direction intersecting the first direction,
the pair of memory structures each comprise:
a plurality of first semiconductor layers stacked in the first direction;
a via wiring which extends in the first direction, and is electrically connected to the plurality of first semiconductor layers;
a plurality of memory portions which are arranged in the first direction corresponding to the plurality of first semiconductor layers, and are electrically connected to the plurality of first semiconductor layers;
a plurality of first gate electrodes which are arranged in the first direction corresponding to the plurality of first semiconductor layers, and face the plurality of first semiconductor layers;
a second semiconductor layer which is provided between the plurality of first semiconductor layers and the first wiring, and is electrically connected to the via wiring;
a connecting electrode which is provided between the plurality of memory portions and the first wiring, and is electrically connected to the second semiconductor layer;
and
a second gate electrode which is provided between the plurality of first gate electrodes and the first wiring, and faces the second semiconductor layer,
the connecting electrode included in one of the pair of memory structures being electrically connected to the first wiring, and
the via wiring included in the one of the pair of memory structures being electrically connected to the via wiring included in the other of the pair of memory structures.

10 more elements

A semiconductor memory device comprising:

a plurality of first semiconductor layers stacked in a first direction;
a via wiring which extends in the first direction, and is electrically connected to the plurality of first semiconductor layers;
a plurality of memory portions which are arranged in the first direction corresponding to the plurality of first semiconductor layers, and are electrically connected to the plurality of first semiconductor layers;
a plurality of first gate electrodes which are arranged in the first direction corresponding to the plurality of first semiconductor layers, and face the plurality of first semiconductor layers;
a first wiring provided on one side in the first direction with respect to the plurality of first semiconductor layers;
a second semiconductor layer which is provided between the plurality of first semiconductor layers and the first wiring, and is electrically connected to the via wiring;
a first connecting electrode which is provided between the plurality of memory portions and the first wiring, and is electrically connected to the first wiring and the second semiconductor layer;
a second gate electrode which is provided between the plurality of first gate electrodes and the first wiring, and faces the second semiconductor layer;
a second wiring provided between the first wiring and the second semiconductor layer;
a third semiconductor layer which is provided between the via wiring and the second wiring, and is electrically connected to the via wiring and the second wiring;
and
a third gate electrode which is provided between the via wiring and the second wiring, and faces an outer peripheral surface of the third semiconductor layer.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/076,096Filed 11 Mar 2025
Priority: JP 2024-16355920 Sep 2024
Published: 26 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10B 12/02
Manufacture or treatment: for one transistor one-capacitor [1T-1C] memory cells
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B
Electronic memory devices

Family

No related US applications are recorded in the indexed filing history.

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