Semiconductor device having high density and high performance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy LIAW
Life of this patent
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Abstract
In a semiconductor device, first to third metal layers are stacked from bottom to top over multiple transistors. Each transistor includes a gate electrode extending in a first direction. Each of multiple metal lines of the first metal layer extends in a second direction, and has a thickness of T1. Each of multiple metal lines of the second metal layer extends in the first direction, and has a thickness of T2. Each of multiple metal lines of the third metal layer extends in the second direction, and has a thickness of T3. One of T2/T1 and T2/T3 is greater than or equal to 1.2.
Claims20
A semiconductor device comprising:
- a substrate;
- a plurality of transistors disposed on the substrate, and each including a gate electrode that extends in a first direction;
- a first metal layer disposed over the transistors, and including a plurality of first metal lines, where each of the first metal lines extends in a second direction transverse to the first direction, and has a thickness of T1;
- a second metal layer disposed over the first metal layer, and including a plurality of second metal lines, where each of the second metal lines extends in the first direction, and has a thickness of T2;
- and
- a third metal layer disposed over the second metal layer, and including a plurality of third metal lines, where each of the third metal lines extends in the second direction, and has a thickness of T3;
- wherein one of T2/T1 and T2/T3 is greater than or equal to 1.2.
A semiconductor device comprising:
- a substrate;
- a plurality of transistors disposed on the substrate, and each including a gate electrode that extends in a first direction;
- a first metal layer disposed over the transistors, and including a plurality of first metal lines, where each of the first metal lines extends in a second direction transverse to the first direction, and the first metal lines have a minimum width of W1;
- a second metal layer disposed over the first metal layer, and including a plurality of second metal lines, where each of the second metal lines extends in the first direction, and the second metal lines have a minimum width of W2;
- and
- a third metal layer disposed over the second metal layer, and including a plurality of third metal lines, where each of the third metal lines extends in the second direction, and the third metal lines have a minimum width of W3;
- wherein each of W2/W1 and W2/W3 is greater than or equal to 1.2.
A semiconductor device comprising:
- a substrate;
- a static random access memory (SRAM) cell disposed on the substrate, and including a plurality of transistors, where each of the transistors includes a gate electrode that extends in a first direction;
- a first metal layer disposed over the SRAM cell, and including a plurality of first metal lines, where each of the first metal lines extends in a second direction transverse to the first direction, and has a thickness of T1;
- a second metal layer disposed over the first metal layer, and including a plurality of second metal lines, where each of the second metal lines extends in the first direction, and has a thickness of T2;
- a third metal layer disposed over the second metal layer, and including a plurality of third metal lines, where each of the third metal lines extends in the second direction, and has a thickness of T3;
- a fourth metal layer disposed over the third metal layer, and including a plurality of fourth metal lines, where each of the fourth metal lines extends in the first direction, and has a thickness of T4;
- and
- a fifth metal layer disposed over the fourth metal layer, and including a plurality of fifth metal lines, where each of the fifth metal lines extends in the second direction, and has a thickness of T5;
- wherein T2 is greater than any one of T1 and T3;
- and
- wherein one of the second metal lines and one of the fourth metal lines are connected to each other, cooperatively serve as a word line, and are further connected to the SRAM cell.
Dependencies are inferred from the claim text.