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US 2026/0089907 A1Published application
BEOL SRAM Devices
AssigneeApple Inc.
InventorsSaurabh P. Sinha, Xin Miao
Life of this patent
Estimating the term…
Abstract
Integrated circuit devices with memory circuits formed between topside BEOL (back end of line) metal layers are described. The memory circuits include active regions and source/drains that can be formed in the spaces between topside metal layers. In certain instances, the memory circuits are formed in between metal layers furthest away from substrate. The memory circuits connect to signal and power routing either above or below the transistors. In various instances, the active regions of the memory circuits are formed by thin channel materials.
Claims20
An apparatus, comprising:
- a transistor region of an integrated circuit, the transistor region being above a substrate in a vertical dimension perpendicular to the substrate;
- a first metal layer located above the transistor region in the vertical dimension, the first metal layer having power supply routing, ground supply routing, and wordline routing oriented along a first direction in a horizontal dimension;
- a second metal layer located above the transistor region in the vertical dimension, the second metal layer having bitline routing oriented along a second direction in the horizontal dimension, the second direction being orthogonal to the first direction;
- and
- a memory circuit positioned between the first metal layer and the second metal layer in the vertical dimension, wherein the memory circuit includes:
- a plurality of active regions including at least one active region of a first type and at least one active region of a second type;
- a plurality of transistors having gates and source/drain regions formed over the plurality of active regions;
- and
- a plurality of vias, wherein the plurality of vias includes at least:
- a first via coupling a first source/drain region to the bitline routing;
- a second via coupling a gate to the wordline routing;
- a third via coupling a second source/drain region to the power supply routing;
- and
- a fourth via coupling a third source/drain region to the ground supply routing.
11 more elements
An apparatus, comprising:
- a transistor circuit positioned within a transistor region of an integrated circuit, the transistor being above a substrate in a vertical dimension perpendicular to the substrate;
- a first metal layer located above the transistor circuit in the vertical dimension, the first metal layer having power supply routing, ground supply routing, and wordline routing oriented along a first direction in a horizontal dimension;
- a second metal layer located above the transistor circuit in the vertical dimension, the second metal layer having bitline routing oriented along a second direction in the horizontal dimension, the second direction being orthogonal to the first direction;
- and
- a memory circuit positioned between the first metal layer and the second metal layer in the vertical dimension, wherein the memory circuit includes:
- a first n-type active region;
- a second n-type active region displaced from the first n-type active region in the horizontal dimension;
- a first p-type active region;
- a second p-type active region displaced from the first p-type active region in the horizontal dimension;
- a set of at least four transistors having gates and source/drain regions formed over the active regions, wherein the gates and the source/drain regions are interconnected to form the memory circuit;
- and
- a plurality of vias coupling the transistors to the bitline routing, the wordline routing, the power supply routing, and the ground supply routing.
9 more elements
An apparatus, comprising:
- a transistor region of an integrated circuit, the transistor region being above a substrate in a vertical dimension perpendicular to the substrate;
- a first metal layer located above the transistor region in the vertical dimension, the first metal layer having ground supply routing and wordline routing oriented along a first direction in a horizontal dimension;
- a second metal layer located above the transistor region in the vertical dimension, the second metal layer having power supply routing oriented along the first direction in the horizontal dimension;
- a third metal layer located above the transistor region in the vertical dimension, the third metal layer having bitline routing oriented along a second direction in the horizontal dimension, the second direction being orthogonal to the first direction;
- and
- a memory circuit positioned between the first metal layer and the second metal layer in the vertical dimension, wherein the memory circuit includes:
- a plurality of active regions including at least one active region of a first type and at least one active region of a second type;
- a plurality of transistors having gates and source/drain regions formed over the plurality of active regions;
- and
- a plurality of vias, wherein the plurality of vias includes at least:
- a first via coupling a first source/drain region to the bitline routing;
- a second via coupling a gate to the wordline routing;
- a third via coupling a second source/drain region to the power routing;
- and
- a fourth via coupling a third source/drain region to the ground routing.
12 more elements
Dependencies are inferred from the claim text.