US 2026/0076257 A1 · SYSTEMS AND METHODS FOR LATERAL STACKING OF DIE

Abstract

Disclosed methods for lateral stacking of die can include positioning a first silicon chip of a semiconductor device horizontally with respect to a second silicon chip of the semiconductor device. The methods can additionally include positioning a third silicon chip of the semiconductor device vertically with respect to both the first silicon chip and the second silicon chip. The disclosed methods can also include electrically connecting the first silicon chip and the second silicon chip by the third silicon chip. Various other methods and systems are also disclosed.

Claims20

Dependent claims

A device comprising:

a first silicon chip of a semiconductor device;
a second silicon chip of the semiconductor device, wherein the second silicon chip is positioned horizontally with respect to the first silicon chip;
and
a third silicon chip of the semiconductor device, wherein the third silicon chip is positioned vertically with respect to both the first silicon chip and the second silicon chip, and the third silicon chip provides an electrical connection between the first silicon chip and the second silicon chip.

1 more element

Dependencies are inferred from the claim text.

Systems and methods for lateral stacking of die

Life of this patent

Systems and methods for lateral stacking of die

Life of this patent

Abstract

Claims20