Semiconductor package with power line

A semiconductor package, comprising:

• a base substrate comprising a first power line;
• a plurality of power bumps in contact with the first power line;
• and
• a semiconductor chip on the plurality of power bumps,
• wherein the first power line comprises:
• a first line wiring part extending in a first direction;
• a second line wiring part extending in the first direction and spaced apart from the first line wiring part in a second direction, the second direction intersecting the first direction;
• and
• a first connection wiring part coupling the first line wiring part with the second line wiring part,
• wherein the plurality of power bumps comprise:
• a plurality of first power bumps in contact with the first line wiring part;
• and
• a plurality of second power bumps in contact with the second line wiring part,
• wherein the plurality of first power bumps comprise a first circuit power bump,
• wherein the plurality of second power bumps comprise a second circuit power bump, and
• wherein the first circuit power bump, the second circuit power bump, and the first connection wiring part at least partially overlap a straight line extending in the second direction.

A semiconductor package, comprising:

• a base substrate;
• a plurality of power bumps on the base substrate;
• a signal bump on the base substrate;
• and
• a semiconductor chip on the plurality of power bumps and the signal bump,
• wherein the base substrate comprises:
• a first power line in contact with the plurality of power bumps;
• and
• a signal line in contact with the signal bump,
• wherein the first power line comprises:
• a first line wiring part extending in a first direction;
• a second line wiring part extending in the first direction and spaced apart from the first line wiring part in a second direction, the second direction intersecting the first direction;
• and
• a connection wiring part coupling the first line wiring part with the second line wiring part,
• wherein the semiconductor chip comprises:
• a first cell power pad at least partially overlapping the first line wiring part;
• a first circuit power pad at least partially overlapping the first line wiring part;
• a second circuit power pad at least partially overlapping the second line wiring part;
• and
• a first signal pad at least partially overlapping the signal line,
• wherein the plurality of power bumps comprise:
• a cell power bump in contact with the first line wiring part and the first cell power pad;
• a first circuit power bump in contact with the first line wiring part and the first circuit power pad;
• and
• a second circuit power bump in contact with the second line wiring part and the second circuit power pad,
• wherein the first signal pad is disposed between the first cell power pad and the first circuit power pad, and
• wherein the signal bump is disposed between the cell power bump and the first circuit power bump.