Memory device and manufacturing method of the memory device

A method of manufacturing a memory device, the method comprising:

• forming, on a substrate, a stack structure including a plurality of sacrificial layers alternately stacked with a plurality of interlayer insulating layers in a first direction;
• forming an opening extending in the first direction in the stack structure, exposing inner surfaces of the plurality of sacrificial layers and inner surfaces of the plurality of interlayer insulating layers;
• forming a plurality of charge trap patterns spaced apart in the first direction, wherein a side surface of a first charge trap pattern among the plurality of charge trap patterns has a first slope with respect to the first direction, and wherein each of the plurality of charge trap patterns is disposed between the inner surfaces of a different one of the plurality of sacrificial layers in the first direction;
• forming a channel layer extending in the first direction between the inner surfaces of the plurality of sacrificial layers and the inner surfaces of plurality of interlayer insulating layers, wherein the channel layer includes a first section extending in the first direction and a second section having the first slope;
• injecting a first impurity into the first section of the channel layer;
• and
• injecting a second impurity into the second section of the channel layer, wherein the second impurity is different from the first impurity.

A memory device comprising:

• a stack structure including a plurality of conductive layers alternately stacked with a plurality of interlayer insulting layers in a first direction;
• a channel layer extending through the stack structure and including a first section including a first impurity and extending in the first direction and a second section including a second impurity and disposed at a first slope with relative to the first direction;
• and
• a charge trap pattern located between the channel layer and a first conductive layer of the plurality of conductive layers, wherein a side surface of the charge trap pattern is parallel to the second section.