Semiconductor package and package module including the same

A semiconductor package, comprising:

• a film substrate comprising a plurality of sprocket holes;
• a plurality of first connection patterns disposed in a first direction on the film substrate;
• a plurality of second connection patterns disposed in the first direction on the film substrate;
• a semiconductor chip between the plurality of first connection patterns and the plurality of second connection patterns;
• a protection pattern on the film substrate and at least partially surrounding the semiconductor chip;
• a plurality of pads between the film substrate and the semiconductor chip;
• a test pattern between the film substrate and the protection pattern;
• a plurality of first lines respectively coupled with the plurality of first connection patterns;
• a plurality of second lines respectively coupled with the plurality of second connection patterns;
• and
• a test line extending from a line of the plurality of second lines and coupled with the test pattern,
• wherein the test line is coupled with:
• the line of the plurality of second lines between the film substrate and the semiconductor chip, and
• the test pattern between the film substrate and the protection pattern, and
• wherein the plurality of sprocket holes are aligned along a second direction that intersects the first direction.

A package module, comprising:

• a circuit substrate;
• a display panel spaced apart from the circuit substrate;
• and
• a plurality of semiconductor packages between the circuit substrate and the display panel, the plurality of semiconductor packages electrically coupling the circuit substrate with the display panel,
• wherein each package of the plurality of semiconductor packages comprises:
• a film substrate comprising a sprocket hole;
• a first connection pattern coupled with the circuit substrate;
• a second connection pattern coupled with the display panel;
• a semiconductor chip on the film substrate;
• a protection pattern on the film substrate and at least partially surrounding the semiconductor chip;
• a plurality of pads between the film substrate and the semiconductor chip;
• a test pattern between the film substrate and the protection pattern;
• a first line coupled with the first connection pattern;
• a second line coupled with the second connection pattern;
• and
• a test line extending from the second line and coupled with the test pattern,
• wherein the test line comprises:
• a first part at least partially overlapping the semiconductor chip;
• and
• a second part between the first line and the second line, and
• wherein the first line and the second line are adjacent to each other.