Lithography scanner throughput
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKai-Chieh Chang, Che-Chang Hsu, Kai-Fa Ho, Li-Jui Chen
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKai-Chieh Chang, Che-Chang Hsu, Kai-Fa Ho, Li-Jui Chen
Estimating the term…
A method and system for optimizing scan speed of a lithography scanner. A process design layout corresponding to a plurality of rows of fields to be formed on an associated wafer is received and a default machine constant of the lithography scanner is determined. Each of the plurality of rows is then identified corresponding to the received process design layout. A scan speed for each determined type of row and the determined default machine constant is then determined. The associated wafer is then processed utilizing the determined scan speed for each of the plurality of rows in accordance with the process design layout.
A method for optimizing scan speed for increased throughput in a lithography device, the lithography device including a reticle assembly stage and a wafer assembly stage, the method comprising:
A method for optimizing scan speed of a lithography scanner device, the lithography scanner device including a reticle assembly stage and a wafer assembly stage, the method comprising:
A system for optimizing scan speed of a lithographic scanner device, the system comprising:
Dependencies are inferred from the claim text.