Three-dimensional memory devices and fabricating methods thereof

A method for forming a semiconductor device, comprising:

• forming a dielectric stack comprising alternative sacrificial layers and dielectric layers;
• forming first through holes laterally aligned along a first lateral direction and each extending vertically through the dielectric stack;
• forming sacrificial filling structures in the first through holes;
• removing the sacrificial filling structures from first subsets of the first through holes;
• forming first dummy contact structures in the first subsets of the first through holes;
• removing the sacrificial filling structures from second subsets of the first through hole to form gate line slits, wherein the first dummy contact structures are located between the gate line slits, the first dummy contact structures and the gate line slits are laterally aligned in the first lateral direction;
• and
• forming gate line slit structure segments in the gate line slits.

A memory device, comprising:

• a stack structure comprising alternative conductive layers and dielectric layers;
• channel structures each vertically extending in an array region of the stack structure;
• a gate line structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory fingers, the gate line structure comprising:
• gate line slit structure segments aligned along the first lateral direction, and
• first dummy contact structures aligned close to each other along the first lateral direction and located between the gate line slit structure segments in the first lateral direction;
• second dummy contact structures aligned discrete with each other and located in a staircase region of the stack structure;
• and
• gate line contact structures extending vertically in the staircase region of the stack structure.