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US 2025/0157973 A1Published application
Systems and methods for reducing semiconductor device delamination
AssigneeAdvanced Micro Devices, Inc.
InventorHsiang-Wei Liu
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Abstract
A method for reducing semiconductor device delamination can include depositing a top barrier layer on top of a metal layer plating a bottom barrier layer. The method can also include depositing dielectric material on top of the top barrier layer and adjacent to the metal layer and the bottom barrier layer. Various other methods and systems are also disclosed.
Claims20
A semiconductor device, comprising:
- a top barrier layer deposited on top of a metal layer plating a bottom barrier layer;
- and
- dielectric material deposited on top of the top barrier layer and adjacent to the metal layer and the bottom barrier layer.
A semiconductor device package, comprising:
- a barrier layer deposited on top of a metal redistribution layer;
- dielectric material deposited on top of the barrier layer absent planarization of the metal redistribution layer;
- and
- a die resting on top of a carrier and electrically connected to the metal redistribution layer.
1 more element
A method comprising:
- depositing a top barrier layer on top of a metal layer plating a bottom barrier layer;
- and
- depositing dielectric material on top of the top barrier layer and adjacent to the metal layer and the bottom barrier layer.
Dependencies are inferred from the claim text.