Systems and methods for dimensioning a land grid array pad

A land grid array, comprising:

• a first plurality of land grid array pads arranged on a first surface region of a side of a semiconductor device package substrate;
• and
• a second plurality of land grid array pads arranged on a second surface region of the side of the semiconductor device package substrate,
• wherein land grid array pads of the first plurality of land grid array pads and the second plurality of land grid array pads have initial landing areas and final landing areas, the initial landing areas have dimensions causing at least a majority of landing surfaces of a plurality of socket pins to land off of the initial landing areas prior to actuation of one or more sockets including the plurality of socket pins, and the final landing areas have dimensions configured to maintain electrical contact with the landing surfaces of the plurality of socket pins after actuation of the one or more sockets including the plurality of socket pins.