Area-optimized cells for low power technology nodes
AssigneeATI Technologies ULC
InventorIoan CORDOS
Life of this patent
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Abstract
Embodiments herein describe identifying voltage potentials in separate cells that can be combined so that a dummy gate between or in the cells can be removed. For example, some combinational logic cells such as XOR gates, XNOR gates, and half-adders are formed from coupling two combinational cells in sequence. Typically, a dummy gate is placed between those cells since they have different voltage potentials. However, if the cells have the same voltage potentials, then the dummy gate can be removed and the cells can overlap by sharing a net. This can reduce the overall size of the cell.
Claims20
An integrated circuit (IC), comprising:
- at least one of an XOR or XNOR circuit comprising at least two cells,
- wherein the two cells overlap such that each of the two cells share at least one net,
- wherein there is no dummy gate between or in either of the two cells.
A system, comprising:
- an IC, comprising:
- at least one of an XOR or XNOR circuit comprising at least two cells,
- wherein the at least two cells overlap,
- wherein there is no dummy gate between or in either of the two cells;
- and
- a memory communicatively coupled to the IC.
A method comprising:
- providing a layout of an XOR or XNOR circuit comprising multiple cells with at least one shared net;
- and
- fabricating an IC that includes the XOR or XNOR circuit using the layout and a 3 nm process or smaller.
Dependencies are inferred from the claim text.