Semiconductor memory device

A semiconductor memory device comprising:

• a substrate including a first area and a second area arranged in a first direction;
• a plurality of conductive layers above the substrate, the conductive layers being arranged in a second direction intersecting the first direction alternately with insulating layers each interposed between adjacent two of the conductive layers;
• a first member and a second member arranged in a third direction intersecting each of the first direction and the second direction, the first member and the second member extending in the first direction across the first area and the second area and dividing the conductive layers;
• and
• a pillar penetrating the conductive layers in the first area,
• wherein
• the second area includes a first contact area interposed between the first member and the second member in the third direction, and a second contact area interposed between the first member and the second member in the third direction and separated from the first contact area in the first direction;
• the conductive layers include a first conductive layer, a second conductive layer above the first conductive layer, a third conductive layer above the second conductive layer, a fourth conductive layer above the third conductive layer, a fifth conductive layer above the fourth conductive layer, a sixth conductive layer above the fifth conductive layer, a seventh conductive layer above the sixth conductive layer, and an eighth conductive layer above the seventh conductive layer, an intersection of the pillar and each of the first to eighth conductive layers in the first area functioning as a memory cell;
• the first conductive layer includes a first terrace portion that does not overlap conductive layers above the first conductive layer of the conductive layers in the first contact area;
• the second conductive layer includes a second terrace portion that does not overlap conductive layers above the second conductive layer of the conductive layers in the first contact area;
• the third conductive layer includes a third terrace portion that does not overlap conductive layers above the third conductive layer of the conductive layers in the second contact area;
• the fourth conductive layer includes a fourth terrace portion that does not overlap conductive layers above the fourth conductive layer of the conductive layers in the second contact area;
• the fifth conductive layer includes a fifth terrace portion that does not overlap conductive layers above the fifth conductive layer of the conductive layers in the first contact area;
• the sixth conductive layer includes a sixth terrace portion that does not overlap conductive layers above the sixth conductive layer of the conductive layers in the first contact area;
• the seventh conductive layer includes a seventh terrace portion that does not overlap conductive layers above the seventh conductive layer of the conductive layers in the second contact area;
• the eighth conductive layer includes an eighth terrace portion that does not overlap conductive layers above the eighth conductive layer of the conductive layers in the second contact area;
• and
• a first contact, a second contact, a third contact, a fourth contact, a fifth contact, a sixth contact, a seventh contact, and an eighth contact extend in the second direction respectively from the first to eighth terrace portions.