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US 2025/0098171 A1Published application
Memory device and electronic apparatus including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKyunghun KIM, Hoseok HEO, Sunho KIM, Seungyeul YANG, Minhyun LEE, Seokhoon CHOI
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Abstract
A memory device includes: a channel layer; a gate electrode spaced apart from the channel layer; and a multilayer charge trap layer disposed between the channel layer and the gate electrode, wherein the multilayer charge trap layer includes silicon oxynitride, the silicon oxynitride including gallium or silicon nitride including gallium.
Claims20
A memory device comprising:
- a channel layer;
- a gate electrode spaced apart from the channel layer;
- and
- a multilayer charge trap layer disposed between the channel layer and the gate electrode,
- wherein the multilayer charge trap layer comprises silicon oxynitride, the silicon oxynitride comprising gallium or silicon nitride comprising gallium.
2 more elements
A memory device comprising:
- a substrate;
- and
- a plurality of memory cell arrays disposed on the substrate,
- wherein each of the plurality of memory cell arrays includes:
- a channel layer extending in a first direction;
- a plurality of gate electrodes spaced apart from the channel layer in a second direction different from the first direction, wherein the plurality of gate electrodes are alternately arranged in the first direction;
- and
- a multilayer charge trap layer disposed between the channel layer and the gate electrode, and
- wherein the multilayer charge trap layer comprises silicon oxynitride, the silicon oxynitride comprising gallium or silicon nitride comprising gallium.
6 more elements
Dependencies are inferred from the claim text.