Memory devices with a backside read word line

A semiconductor structure, comprising:

• a memory cell connected to a write word line and a read word line;
• a first interconnect structure disposed over the memory cell and comprising the write word line;
• and
• a second interconnect structure disposed under the memory cell and comprising the read word line.

A semiconductor structure, comprising:

• a first memory cell comprising:
• a write port portion;
• and
• a read port portion comprising a transistor having a first source/drain feature and a second source/drain feature coupled to a channel region, and a gate structure engaging the channel region,
• a backside via disposed directly under and in direct contact with the gate structure;
• and
• a first interconnect layer disposed under and electrically coupled to the backside via, wherein a read word line is positioned at the first interconnect layer.