Microelectronic devices including slit structures, and related memory devices

A memory device, comprising:

• a stack structure comprising levels of conductive material vertically alternating with levels of insulative material;
• a source structure below the stack structure and comprising a lateral contact region including doped polycrystalline silicon vertically interposed between two additional regions thereof;
• strings of memory cells vertically extending through the stack structure and respectively having a channel material coupled to the doped polycrystalline silicon of the lateral contact region of the source structure;
• and
• dielectric-filled slots horizontally extending in parallel in a first direction and vertically extending completely through the stack structure and into the source structure, the dielectric-filled slots respectively comprising side boundaries having a non-planar topography within a vertical extent of the source structure.

A 3D NAND Flash memory device, comprising:

• blocks horizontally extending in parallel in a first direction and respectively comprising tiers individually including conductive material vertically neighboring insulative material;
• a source structure vertically underlying the blocks;
• slot structures horizontally extending in parallel in the first direction and horizontally alternating with the blocks in a second direction orthogonal to the first direction, lower portions of the slot structures vertically extending into the source structure and each comprising:
• an upper region;
• a lower region;
• and
• a middle region vertically interposed between the upper region and the lower region, the middle region having a greater horizontal width in the second direction than each of the upper region and the lower region;
• and
• cell pillars within horizontal areas of the blocks and respectively including semiconductor material vertically extending through one of the blocks and into the source structure, vertically lowermost ends of the cell pillars substantially coplanar with vertically lowermost boundaries of the slot structures.