Ferroelectric memory device and method for forming the same

A memory device, comprising:

• a plurality of memory cells, each memory cell comprising:
• at least one first transistor;
• at least one first interconnection layer formed over the at least one first transistor and in electrical contact with the at least one first transistor;
• a first conductive layer formed over the at least one first interconnection layer, the first conductive layer electrically coupled to the at least one first transistor through the at least one first interconnection layer;
• and
• at least one capacitor formed on the first conductive layer, comprising:
• a first electrode;
• a second electrode surrounding at least a first portion of the first electrode, the second electrode electrically contacting the first conductive layer;
• and
• a ferroelectric layer disposed between the first electrode and the second electrode;
• and
• a periphery circuit configured to control operations of the plurality of memory cells,
• wherein the first electrode of the plurality of memory cells functions as a routing structure between the plurality of memory cells.

A method for forming a ferroelectric memory, comprising:

• forming a semiconductor structure over a substrate, the semiconductor structure comprising a cell region and a periphery region;
• forming a first interconnection structure over the cell region of the semiconductor structure and a second interconnection structure over the periphery region of the semiconductor structure;
• forming a dielectric layer over the first interconnection structure and the second interconnection structure;
• forming a capacitor in the dielectric layer above the first interconnection structure and a via structure in the dielectric layer above the second interconnection structure;
• and
• forming a routing structure over the capacitor and the via structure.