Vertical non-volatile memory devices and methods for manufacturing the same

A vertical non-volatile memory device, comprising:

• a cell substrate;
• a mold structure that includes a first gate electrode, an insulation pattern, and a second gate electrode which are sequentially stacked on the cell substrate;
• a semiconductor pattern that extends through the mold structure in a first direction intersecting a top surface of the cell substrate;
• a first charge storage layer between the first gate electrode and the semiconductor pattern;
• a second charge storage layer spaced apart from the first charge storage layer and between the second gate electrode and the semiconductor pattern;
• a first blocking insulation layer between the first gate electrode and the first charge storage layer;
• and
• a second blocking insulation layer spaced apart from the first blocking insulation layer and between the second gate electrode and the second charge storage layer,
• wherein a first distance between the first charge storage layer and the second charge storage layer is shorter than a second distance between the first gate electrode and the second gate electrode.

A method of manufacturing a vertical non-volatile memory device, the method comprising:

• alternately forming a first sacrificial layer, an insulation pattern, and a second sacrificial layer on a cell substrate;
• forming a hole by etching the first sacrificial layer, the insulation pattern, and the second sacrificial layer;
• forming a first blocking insulation layer on the first sacrificial layer and forming a second blocking insulation layer that is spaced apart from the first blocking insulation layer and is on the second sacrificial layer;
• forming a preliminary charge storage layer on the insulation pattern, the first blocking insulation layer, and the second blocking insulation layer;
• forming a blocking pattern on the preliminary charge storage layer in a first region, the first region overlapping the insulation pattern;
• forming a mask on the preliminary charge storage layer in a second region, the second region being free of the blocking pattern;
• and
• performing an etching process to form a first charge storage layer and a second charge storage layer which are separated from each other.