A memory device that uses a semiconductor element, in which a page is made up of a plurality of memory cells arranged in a row direction on a substrate in planar view, the plurality of memory cells are connected to a bit line disposed in a column direction, a memory cell array is made up of a plurality of the pages and a plurality of the bit lines, and the memory device is made up of at least one memory cell array, wherein:
- each of the memory cells contained in the respective pages includes:
- the substrate,
- a first semiconductor layer placed on the substrate,
- a first impurity layer placed on part of a surface of the first semiconductor layer, at least part of the first impurity layer being columnar in shape,
- a second semiconductor layer extending in a vertical direction by being placed in contact with a columnar part of the first impurity layer,
- a first insulating layer covering part of the first semiconductor layer and part of the first impurity layer,
- a first gate insulating layer surrounding the first impurity layer and the second semiconductor layer by being placed in contact with the first insulating layer,
- a first gate conductor layer placed in contact with the first insulating layer and the first gate insulating layer,
- a second insulating layer formed in contact with the first gate conductor layer and the first gate insulating layer,
- a third semiconductor layer placed in contact with the second semiconductor layer,
- a second gate insulating layer partially or entirely surrounding an upper part of the third semiconductor layer,
- a second gate conductor layer partially or entirely covering an upper part of the second gate insulating layer, and
- a second impurity layer and a third impurity layer placed, respectively, in contact with opposing lateral surfaces of the third semiconductor layer located on an outer side of one end of the second gate conductor layer in a horizontal direction in which the third semiconductor layer extends;
- the second impurity layer is connected with a source line, the third impurity layer is connected with a bit line, the second gate conductor layer is connected with a word line, and the first gate conductor layer is connected with a plate line;
- a page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line;
- the page erase operation involves extracting electron groups or positive hole groups whichever are majority carriers remaining in the second semiconductor layer or the third semiconductor layer by recombining the electron groups or the positive hole groups with majority carriers in the first impurity layer, the second impurity layer, and the third impurity layer;
- the page write operation involves an operation of generating the electron groups and the positive hole groups in the third semiconductor layer and the second semiconductor layer using a gate induced drain leakage current, an operation of removing the generated electron groups or the positive hole groups whichever are minority carriers in the third semiconductor layer and the second semiconductor layer, and an operation of causing part or all of the electron groups or the positive hole groups whichever are majority carriers in the third semiconductor layer and the second semiconductor layer to remain in the third semiconductor layer and the second semiconductor layer;
- and
- the page read operation involves determining whether the memory cell is in an erased state or a written state based on a magnitude relationship between memory cell currents flowing through the bit line and the source line of the memory cell.