Semiconductor device and manufacturing method thereof

A semiconductor device comprising:

• a source line extending in a first horizontal direction on a substrate;
• a word line disposed at a vertical level higher than the source line and extending in a second horizontal direction crossing the first horizontal direction;
• a gate insulating layer disposed on an inner wall of a word line opening penetrating the word line and extending in a vertical direction perpendicular to an upper surface of the substrate;
• a trap layer disposed on the gate insulating layer disposed on the inner wall of the word line opening;
• a channel layer disposed on the trap layer disposed on the gate insulating layer disposed on the inner wall of the word line opening and having a part in contact with an upper surface of the source line on a bottom portion of the word line opening;
• a drain area disposed at a vertical level higher than the word line, contacting an upper surface of the channel layer, and comprising a material having a work function equal to or smaller than 4.2 eV;
• and
• a bit line disposed on the drain area and connected in the first horizontal direction.

A semiconductor device comprising:

• a plurality of source lines extending in a first horizontal direction on a substrate;
• a plurality of word lines respectively disposed at a vertical level higher than the plurality of source lines and extending in a second horizontal direction crossing the first horizontal direction;
• a plurality of bit lines respectively disposed at a vertical level higher than the plurality of word lines and extending in the first horizontal direction;
• and
• a plurality of memory units respectively disposed at intersections of the plurality of word lines and the plurality of bit lines;
• wherein each of the plurality of memory units comprises,
• a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate and contacting an upper surface of a source line of the plurality of source lines;
• a trap layer disposed on an outer wall of the channel layer;
• a gate insulating layer disposed on an outer wall of the trap layer and surrounded by a word line of the plurality of word lines;
• and
• a drain area disposed on an upper surface of the channel layer and below each of the plurality of bit lines and including a metal or metal nitride.