Apparatus and method to reduce memory power consumption in a memory phy in a memory controller

Abstract

Memory power consumption is reduced without increasing latency of memory read access. When inactive, power consumption is reduced in a PHY in a memory controller by disabling receiver bias circuitry and a clock network in the PHY. The memory controller sends two command-based signals to the PHY to enable the PHY to enable the receiver bias circuitry and the clock network in the PHY to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. A first command-based signal is an early command indication signal that is sent before any command. The second command-based signal is a read indication signal that is sent synchronous with every read command. Upon receiving these signals, the PHY enables the clock network and receiver bias circuitry.

Dependencies are inferred from the claim text.