One-time programmable memory device

An one-time programmable (OTP) memory array, comprising:

• a plurality of OTP memory cells arranged in a plurality of columns and a plurality of rows, each OTP memory cell comprising:
• an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line configured to receive a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal;
• and
• a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line configured to receive a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal;
• wherein the antifuse transistor of at least one of the plurality of OTP memory cells has a first terminal that is a vacancy terminal and a second terminal that is connected to the selection transistor.

A method of fabricating an one-time programmable (OTP) memory cell, comprising:

• fabricating an antifuse transistor, wherein a first terminal of the antifuse transistor is a vacancy terminal;
• fabricating a selection transistor;
• connecting a second terminal of the antifuse transistor to the selection transistor;
• connecting a gate terminal of the antifuse transistor to a first word line configured to receive a first signal, wherein the antifuse transistor is selectable between a first state and a second state in response to the first signal;
• connecting a gate terminal of the selection transistor to a second word line configured to receive a second signal, wherein the selection transistor is configured to provide access to the antifuse transistor in response to the second signal;
• and
• connecting the selection transistor to a bit line.