Small-area and low-voltage anti-fuse element and array

A small-area and low-voltage anti-fuse array, comprising

• a plurality of parallel bit lines, including a first bit line;
• a plurality of parallel word lines, vertical to said bit lies, and including a first word line and a second word line, which are respectively disposed on two sides of said first bit line;
• a plurality of parallel select lines, parallel to said word lines, and including a first select line and a second select line, which respectively neighbor said first word line and said second word line;
• a plurality of anti-fuse elements, wherein each said anti-fuse element is connected with two said word lines, two said select lines and one said bit line, and including
• four first gate dielectric layers, each two formed symmetrically on a substrate along said first bit line;
• an anti-fuse gate, disposed on said first gate dielectric layer, wherein four corners of said anti-fuse gate respectively overlap corners of said first gate dielectric layers, which are closest to said anti-fuse gate;
• each of said four corners of said anti-fuse gate is fabricated to have at least one sharp angle;
• said anti-fuse gate is connected with said first bit line;
• four first ion-doped areas, each formed in a region of said substrate, which is in one side of one said first gate dielectric layer;
• two said first ion-doped areas on the same side of said first bit line are respectively connected with said first select line and said second select line;
• and
• four select transistors, respectively neighboring said first ion-doped areas, and each including
• a second gate dielectric layer, formed on said substrate;
• a select gate, stacked over said second gate dielectric layer;
• and
• a second ion-doped area, formed in a region of said substrate, which is in one side of said second gate dielectric layer, wherein said one side of said second dielectric layer is far away from said first ion-doped area;
• said second ion-doped area and said first ion-doped area are doped with an identical type of ions;
• wherein two said select gates of two said select transistors on the same side of said first bit line are respectively connected with said first word line and said second word line;
• two said second ion-doped areas on the same side of said first bit line are respectively connected with said first select line and said second select line.