Semiconductor device having staggered gate-stub-size profile and method of manufacturing same

A method of manufacturing a semiconductor device, for which a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged into rows which extend substantially in a first direction and being populated correspondingly with cells, the layout diagram including active area patterns, gate patterns, via-to-gate (VG) patterns and cut-gate patterns, the active area patterns and the cut-gate patterns extending substantially in the first direction, the gate patterns extending substantially in a second direction which is substantially perpendicular to the first direction, each VG pattern overlying a corresponding one of the gate patterns, the cut-gate patterns overlying corresponding row boundaries, each cut-gate pattern being organized in the first direction into sections (cut-gate sections), each cut-gate section extending substantially in the first direction and straddling a corresponding one of the gate patterns relative to the first direction, each cut-gate section indicating that any underlying portion of the corresponding gate pattern is designated for removal, the method comprising generating the layout diagram including:

• for each of the gate patterns, and relative to the second direction, and further relative to corresponding first and second ones of the cells which abut at a corresponding row boundary, and further relative to first and second ones of the active area patterns which correspondingly are in the first and second cells and which are nearest to the corresponding row boundary (first and second nearest active area patterns),
• increasing a size of the corresponding cut-gate section from a first value to a second value,
• the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern;
• and
• the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern;
• relative to the second direction,
• selecting ones among the gate patterns for which a first distance from the corresponding VG pattern to the corresponding cut-gate section is less than a first reference value;
• and
• for each of the selected gate patterns, and
• relative to the second direction, and with a size of the corresponding cut-gate section being measured from the corresponding row boundary,
• reverting the size of the corresponding cut-gate section from the second value to the first value;
• the second value resulting in a first type of overhang of the corresponding remnant portion;
• and
• the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern.

A semiconductor device comprising:

• active regions extending substantially in a first direction;
• gate electrodes which extend substantially in a second direction which is substantially perpendicular to the first direction and which overlie corresponding portions of the active regions;
• and
• via-to-gate (VG) structures, each VG structure overlying a corresponding one of the gate electrodes;
• and
• wherein:
• the gate electrodes are arranged into pairs of corresponding first and second ones of the gate electrodes;
• and
• for each pair:
• the first and second gate electrodes are substantially collinear and separated by a corresponding first gap;
• the first and second gate electrodes overlap corresponding first and second ones of the active regions which are nearest the first gap;
• and
• first and second stubs of the corresponding first and second gate electrodes correspondingly extend beyond the first and second active regions into the first gap correspondingly by substantially a first distance or a second distance, the second distance being smaller than the first distance, resulting in a staggered stub-size profile.