Method of manufacturing a semiconductor device with self-aligning landing pad

Abstract

A method of manufacturing a semiconductor memory device includes providing a substrate with a drain, a source and a gate structure disposed on the substrate between the drain and the source; forming a first inter-layer dielectric covering the substrate and the gate structure; forming a plug in the first inter-layer dielectric, with a first part contacting the source of the substrate. In the next step, a second part of the plug is exposed through the first inter-layer dielectric, and a storage node landing pad is formed on the exposed second part of the plug; a second inter-layer dielectric is formed on the first inter-layer dielectric, covering the storage node landing pad; a bit line is formed, connected to the substrate through the second inter-layer dielectric and the first inter-layer dielectric; a third inter-layer dielectric is formed on the bit line; and, a storage node is formed on the third inter-layer dielectric.

Dependencies are inferred from the claim text.