Embedded MRAM Device with Top Via

A method of forming an embedded MRAM device, the method comprising the steps of:

• depositing a cap layer onto a substrate, wherein the substrate comprises a logic-to-memory boundary area separating a logic area of the substrate from a memory area of the substrate;
• forming a metal line on the cap layer over the logic area of the substrate, and a metal pad on the dielectric cap layer over the memory area of the substrate;
• patterning i) the metal line to form first top vias over an unpatterned portion of the metal line, and ii) the metal pad to form a second top via over an unpatterned portion of the metal pad;
• depositing a dielectric material onto the substrate surrounding the first top vias and the second top via;
• recessing the second top via and the dielectric material in the memory area of the substrate, wherein following the recessing what remains of the second top via serves as a bottom contact via that is self-aligned to the unpatterned portion of the metal pad which serves as a bottom contact;
• forming an MRAM stack on the dielectric material over the first top vias in the logic area of the substrate and over the bottom contact via in the memory area of the substrate, wherein the MRAM stack comprises a bottom electrode layer, an MTJ layer disposed on the bottom electrode layer, and a top electrode layer disposed on the MTJ layer;
• patterning the MRAM stack to form an MRAM cell over the bottom contact via in the memory area of the substrate;
• depositing an ILD onto the dielectric material over the first top vias and the MRAM cell;
• recessing the ILD to expose the first top vias and the MRAM cell;
• and
• forming first top contacts and a second top contact over the ILD, wherein the first top contacts are in contact with the first top vias and the second top contact is in contact with the MRAM cell.

An embedded MRAM device, comprising:

• a substrate comprising a logic-to-memory boundary area separating a logic area of the substrate from a memory area of the substrate;
• a cap layer disposed on the substrate;
• a metal line disposed on the cap layer over the logic area of the substrate;
• a metal pad disposed on the cap layer over the memory area of the substrate;
• top vias formed on the metal line;
• a bottom contact via self-aligned to the metal pad, wherein the metal pad serves as a bottom contact of the MRAM device;
• a dielectric material disposed on the substrate over the metal line and the metal pad and surrounding the top vias and the bottom contact via;
• an MRAM cell formed over the bottom contact via in the memory area of the substrate;
• spacers along sidewalls of the MRAM cell, wherein the spacers comprise a material selected from the group consisting of:
• SiN, SiCN, SiCNH, and combinations thereof;
• first top contacts in contact with the top vias;
• and
• a second top contact in contact with the MRAM cell.