Semiconductor memory devices having stacked structures therein that support high integration

A semiconductor memory device, comprising:

• a horizontal conductive layer on a substrate;
• a lower stack structure on the horizontal conductive layer, said lower stack structure comprising an alternating vertical arrangement of a plurality of lower insulating layers and a plurality of lower electrode layers;
• an upper stack structure disposed on the lower stack structure, said upper stack structure comprising an alternating vertical arrangement of a plurality of upper insulating layers and a plurality of upper electrode layers;
• a channel structure extending through the upper stack structure and the lower stack structure and into an inside of the horizontal conductive layer;
• and
• a bit line on the upper stack structure, which is electrically connected the channel structure;
• wherein a first one of the lower electrode layers disposed nearest an interface between the lower stack structure and the upper stack structure relative to all other ones of the lower electrode layer is thicker than a second one of the lower electrode layers, which extends between the first lower electrode layer and the substrate;
• and
• wherein at least one of the plurality of lower insulating layers and the plurality of upper insulating layers directly contacts the interface.

A semiconductor device, comprising:

• a horizontal conductive layer disposed on a substrate;
• a lower stack structure disposed on the horizontal conductive layer, the lower stack structure comprising a plurality of lower insulating layers and a plurality of lower electrode layers which are alternately repeatedly stacked;
• an upper stack structure disposed on the lower stack structure, the upper stack structure comprising a plurality of upper insulating layers and a plurality of upper electrode layers which are alternately repeatedly stacked;
• a channel structure extending through the upper stack structure and the lower stack structure and into an inside of the horizontal conductive layer;
• and
• a bit line disposed on the upper stack structure and electrically connected to the channel structure;
• wherein a first upper electrode layer disposed nearest an interface between the lower stack structure and the upper stack structure relative to all other ones of the plurality of upper electrode layers is thicker than a second upper electrode layer extending adjacent a center of the upper stack structure;
• and
• wherein at least one of the plurality of lower insulating layers and the plurality of upper insulating layers directly contacts the interface.