A 3d semiconductor wafer, devices, and structure

A 3D semiconductor wafer, the wafer comprising:

• a first device,
• wherein said first device comprises a first level, said first level comprising first transistors, and
• wherein said first device comprises a second level, said second level comprising first interconnections;
• a second device overlaying said first device,
• wherein said second device comprises a third level, said third level comprising second transistors, and
• wherein said second device comprises a fourth level, said fourth level comprising second interconnections;
• a thermal isolative layer disposed between said first device and said second device,
• wherein said isolative layer has a thermal conductivity less than 0.5 W/m-K,
• wherein said first device is substantially larger in area than said second device;
• and
• a plurality of connection paths,
• wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors.

A 3D semiconductor wafer, the wafer comprising:

• a first device,
• wherein said first device comprises a first level, said first level comprising first transistors, and
• wherein said first device comprises a second level, said second level comprising first interconnections;
• a second device overlaying said first device,
• wherein said second device comprises a third level, said third level comprising second transistors, and
• wherein said second device comprises a fourth level, said fourth level comprising second interconnections;
• a third device overlaying said second device,
• wherein said third device comprises a fifth level, said fifth level comprising third transistors,
• wherein said third device comprises a sixth level, said sixth level comprising third interconnections,
• wherein said first device is substantially larger in area than said second device;
• a plurality of first connection paths,
• wherein said plurality of first connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors;
• and
• a plurality of second connection paths,
• wherein said plurality of second connection paths provides connections from a plurality of said second transistors to a plurality of said third transistors,
• wherein said first connections paths comprise first vertical connections connecting from said first interconnection level to said second interconnections,
• wherein said second connections paths comprise second vertical connections connecting from said second interconnection level to said third interconnections, and
• wherein said first vertical connections or said second vertical connections comprise through layer vias having a circumscribed diameter of less than 400 nm.