Integrated ESD Protection Circuit for GaN Based Device

An electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured to protect a gate terminal of the GaN based transistor during an ESD surge event, the ESD protection circuit comprising:

• a first ESD protection stage comprising a first ESD protection path between a gate terminal and a source terminal of the GaN based transistor, configured to be biased by a gate input voltage of the GaN based transistor, wherein the first ESD protection path is triggered when the gate input voltage is greater than a first trigger threshold;
• and
• a second ESD protection stage operably associated with the first ESD protection stage, comprising a second ESD protection path between the gate terminal and the source terminal of the GaN based transistor, the second ESD protection path being triggered when the gate input voltage is greater than a second trigger threshold;
• wherein the gate input voltage of the GaN based transistor is reduced during the ESD surge event.

A method of protecting a gate terminal of a GaN based transistor during an ESD surge event, comprising:

• biasing the gate terminal of the GaN based transistor with a gate input voltage;
• triggering a first ESD protection path in response to the gate input voltage that is greater than a first trigger threshold;
• triggering a second ESD protection path that being associated with the first ESD protection path, in response to the gate input voltage that is greater than a second trigger threshold;
• and
• reducing the gate input voltage through a clamping process between the first ESD protection path and the second ESD protection path.