Overlay sampling reduction

An apparatus comprising:

• a processor;
• and
• a memory including computer program code for one or more programs, the memory and the computer program code configured to, with the processor, cause the apparatus to perform the following,
• provide a wafer having plural sets of four fields, each field having four corners and the four fields of each set sharing a common vertex;
• measure overlay values near each corner of each field of each set, except for a corner near the common vertex of a first field and a corner near the common vertex of a second field of each set;
• decompose the measured overlay values into measured interfield correctable and non-correctable errors and measured intrafield correctable and non-correctable errors;
• form a virtual stack of all fields of the wafer by way of wafer modeling software;
• determine an average intrafield correctable error and an average intrafield non-correctable error for each corner of the virtual stack based on the measured intrafield correctable and non-correctable errors, respectively;
• and
• predict the overlay values for the corners near the common vertex of the first and second fields of each set based on combinations of the measured interfield correctable and non-correctable errors, the average intrafield correctable errors, and the average non-correctable errors.

A method comprising:

• providing a wafer having plural sets of four fields, each field having four corners and the four fields of each set sharing a common vertex;
• measuring overlay values near each corner of each field of each set, except for a corner near the common vertex of a first field and a corner near the common vertex of a second field of each set;
• distributing evenly among the plural sets of four fields the corner near the common vertex of the first field and the corner near the common vertex of the second field of each set that are not measured;
• decomposing the measured overlay values into measured interfield correctable and non-correctable errors and measured intrafield correctable and non-correctable errors;
• forming a virtual stack of all fields of the wafer by way of wafer modeling software;
• determining an average intrafield correctable error and an average intrafield non-correctable error for each corner of the virtual stack based on the measured intrafield correctable and non-correctable errors, respectively;
• and
• predicting the overlay values for the corners near the common vertex of the first and second fields of each set based on combinations of the measured interfield correctable and non-correctable errors, the average intrafield correctable errors, and the average non-correctable errors.