3d nand memory with decoder and local word line drivers

Abstract

A memory device includes a plurality of stacks of conductive strips, a plurality of conductive vertical structures arranged orthogonally to the plurality of stacks, memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of conductive vertical structures, multiples pluralities of conductive lines, and control circuitry. The plurality of stacks of conductive strips alternate with insulating strips, including at least a bottom layer of conductive strips, a plurality of intermediate layers of conductive strips, and a top layer of conductive strips. A first plurality of conductive lines electrically couple to the top layer of the conductive strips. A second plurality of conductive lines and a third plurality of conductive lines electrically couple to the plurality of intermediate layers. The control circuitry causes the first plurality of conductive lines to select at least a first particular stack in the plurality of stacks, the second plurality of conductive lines to select at least the first particular stack in the plurality of stacks, and the third plurality of conductive lines to select at least one particular layer in the plurality of intermediate layers.

Dependencies are inferred from the claim text.