Methodology for pattern density optimization

A method for pattern density optimization, comprising:

• forming an integrated chip (IC) design comprising a graphical representation of an integrated chip using a computation element;
• performing an initial data preparation process to add one or more assist features to shapes within the IC design using a data preparation element;
• identifying one or more low-pattern-density areas of the IC design having a pattern density below a pre-determined threshold value after performing the initial data preparation process using a local density checking element, wherein respective low-pattern-density areas comprise a subset of the IC design;
• adjusting the pattern density within the one or more low-pattern-density areas by adding one or more dummy shapes within the one or more low-pattern-density areas without adding dummy shapes outside of the one or more low-pattern-density areas using a dummy shape insertion element;
• and
• performing a second data preparation process on the IC design that modifies shapes of the one or more dummy shapes within the one or more low-pattern-density areas using the data preparation element.

An EDA (Electronic design automation) tool, comprising:

• a design tool configured to form an integrated chip (IC) design comprising a graphical representation of an integrated chip;
• a local density checking element configured to identify one or more low-pattern-density areas of a modified IC design having a pattern density that results in a processing failure, wherein respective low-pattern-density areas comprise a subset of the modified IC design;
• a data preparation element configured to perform an initial data preparation process on the IC design to generate the modified IC design having modified shapes of the IC design prior to identifying the one or more low-pattern-density areas, and to further perform a second data preparation process on the IC design that modifies shapes of the one or more dummy shapes within the one or more low-pattern-density areas;
• and
• a dummy shape insertion element configured to adjust the pattern density of the modified IC design within the one or more low-pattern-density areas by adding one or more dummy shapes within the one or more low-pattern-density areas.