Fin field effect transistor with dielectric isolation and anchored stressor elements

A method of forming a semiconductor structure comprising:

• forming a first semiconductor fin and a second semiconductor fin on a top surface of a stack, from bottom to top, of a semiconductor substrate and an insulator layer;
• forming a first gate stack and a second gate stack over said first semiconductor fin and said second semiconductor fin, respectively;
• forming a first trench and a second trench through said insulator layer and into an upper portion of said semiconductor substrate by etching unmasked portions of said first semiconductor fin and said insulator layer employing a combination of at least a patterned mask layer and said first gate stack as an etch mask, wherein said first trench is formed on one side of said first gate stack and said second trench is formed on another side of said gate stack;
• forming a first source region in said first trench, on a first end wall of a remaining portion of said first semiconductor fin, and on a first portion of said semiconductor substrate, and a first drain region in said second trench, on a second end wall of said remaining portion of said semiconductor fin, and on a second portion of said semiconductor substrate;
• and
• forming a second source region and a second drain region on a remaining portion of said second semiconductor fin, wherein said second source region and said second drain region are vertically spaced from said semiconductor substrate by said insulator layer.