Apparatuses and methods of communicating differential serial signals including charge injection

An apparatus, comprising:

• a termination circuit coupled to differential communication paths, wherein the termination circuit is configured to provide a differential termination to a common mode node, the termination circuit including:
• a transistor stack connected between a VDD node and a VSS node to determine a common mode potential on the common mode node between a VDD potential on the VDD node and a VSS potential on the VSS node;
• a first resistance between and directly connected to both a first one of the differential communication paths and the common mode node;
• and
• a second resistance between and directly connected to both a second one of the differential communication paths and the common mode node.

An apparatus, comprising:

• a termination circuit including:
• a transistor stack comprising a transistor of a first doping type and transistor of a second doping type to provide a common mode node;
• a first resistance between a first one of differential communication paths and the common mode node;
• and
• a second resistance between a second one of the differential communication paths and the common mode node.

An apparatus, comprising:

• chip electronics configured to provide parallel communication signals;
• a serializer configured to convert the parallel communication signals from the chip electronics into differential serial signals;
• a transmitter circuit configured to drive the differential communication paths;
• and
• a termination circuit coupled to the differential communication paths, wherein the termination circuit is configured to provide a differential termination to a common mode node, wherein the termination circuit includes:
• a transistor stack comprising first and second transistors to provide the common mode node, wherein the transistor stack is connected between a VDD node and a VSS node to determine a common mode potential on the common mode node between a VDD potential on the VDD node and a VSS potential on the VSS node;
• a first resistance between a first one of the differential communication paths and the common mode node;
• and
• a second resistance between a second one of the differential communication paths and the common mode node.