Methods and Apparatus for Reduced Gate Resistance FinFET

An integrated circuit comprising:

• at least one circuit formed of a plurality of metal gate transistors, each further comprising:
• a plurality of semiconductor fins formed over a semiconductor substrate, the semiconductor fins being arranged in parallel and spaced apart;
• a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins and extending over the semiconductor substrate between the semiconductor fins;
• an interlevel dielectric layer overlying the metal containing gate electrode and the semiconductor substrate;
• a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the metal containing gate electrode;
• and
• a low resistance metal strap formed over the interlevel dielectric layer and coupled to the metal containing gate electrode by the plurality of contacts.

A method comprising:

• forming multiple semiconductor fins over a semiconductor substrate, the multiple semiconductor fins spaced apart;
• forming a metal containing gate electrode overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins;
• forming an interlevel dielectric layer overlying the metal containing gate electrode and the semiconductor substrate;
• forming a plurality of contacts extending through the interlevel dielectric layer to the metal containing gate electrode, each of the plurality of contacts spaced from the channel gate regions of the semiconductor fins;
• and
• forming a metal strap layer over the interlevel dielectric layer coupled to the metal containing gate electrode through the plurality of contacts.