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US 2013/0092987 A1Published application
Mos transistor with no hump effect
AssigneeSTMicroelectronics (Rousset) SAS
InventorLaurent Lopez
Life of this patent
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Abstract
A MOS transistor formed in an active area of a semiconductor substrate and having a polysilicon gate doped according to a first conductivity type, the gate including two lateral regions of the second conductivity type.
Claims19
A device, comprising:
- a semiconductor substrate;
- an active area defined in the semiconductor substrate, the active area having first and second edges opposite to each other;
- and
- a gate positioned on the semiconductor substrate over the active area, the gate having first and second edges that extend transversely with respect to the first and second edges of the active area and are on opposite sides of the gate, a central region doped according to a first conductivity type, and first and second lateral regions doped according to a second conductivity type and spaced apart from each other by the central region, the first and second lateral regions being spaced apart from the first and second edges of the of the gate.
1 more element
A method, comprising:
- manufacturing a MOS transistor in an active area of a semiconductor substrate, the active area having first and second edges opposite to each other, the manufacturing including:
- forming a gate on a surface of the active area, the gate having first and second edges that extend transversely with respect to the first and second edges of the active area and are on opposite sides of the gate;
- implanting first dopant elements in a central region of the gate according to a first conductivity type;
- and
- implanting second dopant elements in first and second lateral regions of the gate according to a second conductivity type, the lateral regions being spaced apart from each other by the central regions, the first and second lateral regions being spaced apart from the first and second edges of the of the gate.
2 more elements
A MOS transistor, comprising:
- a semiconductor substrate that includes a channel region and source and drain regions positioned at opposite first and second sides of the channel region and having a first type of conductivity;
- a gate positioned over the channel region and including first and second edges that extend substantially parallel to the first and second sides of the channel region and are on opposite sides of the gate, a central region the first type of conductivity, and a first lateral region doped according to a second conductivity type and spaced apart from the first and second edges of the gate.
Dependencies are inferred from the claim text.