Embedded capacitor and method of fabricating the same

A method of forming a semiconductor device with one or more vertical three dimensional metal-insulator-metal (MIM) capacitors, the method comprising:

• providing an insulator material layer over a substrate;
• etching a plurality of capacitor vias in an embedded capacitor area of the insulator material layer and a plurality of standard interconnect vias in a standard interconnect area;
• depositing a contact material fill in the plurality of capacitor vias to form a first set of capacitor contacts and in the plurality of standard interconnect vias to form a plurality of standard interconnect contacts;
• etching the insulator material layer adjacent each of the first set of contacts to form a plurality of adjacent voids;
• depositing a dielectric material layer over the standard interconnect area, the plurality of adjacent voids and the first set of capacitor contacts;
• etching away the dielectric material layer that overlies the standard interconnect area;
• and
• depositing a contact material fill in the plurality of voids to form a second set of capacitor contacts that are interleaved with the first set of capacitor contacts.

A semiconductor device having a vertical three dimensional metal-insulator-metal (MIM) capacitor, the capacitor comprising:

• a first contact plate;
• a second contact plate;
• a first set of contacts connected to the first contact plate and extending through an insulator layer toward the second contact plate;
• a second set of contacts connected to the second contact plate and extending through the insulator layer toward the first contact plate, such that the first set of contacts and the second set of contacts are interleaved with one another;
• and
• a dielectric material that wraps around three sides of a contact of the second set of contacts to three sides of a contact of the first set of contacts in an alternating configuration across the length of the capacitor