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US 2012/0258592 A1Published application
Layouts of POLY Cut Openings Overlapping Active Regions
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJung-Hsuan Chen, Yen-Huei Chen, Li-Chun Tien, Hung-Jen Liao
Life of this patent
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Abstract
A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
Claims20
A method comprising:
- forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate;
- forming a first opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the first opening;
- and
- removing the portion of the gate electrode line through the first opening.
1 more element
A method comprising:
- blanket forming a mask layer over a semiconductor wafer comprising:
- a plurality of gate electrode lines comprising dummy gate electrode lines and active gate electrode lines, wherein the plurality of gate electrode lines are parallel to each other and have a uniform pitch;
- a well region;
- a well pickup region of the well region, wherein the well pickup region comprises a portion between two neighboring ones of the plurality of gate electrode lines;
- and
- an active region, wherein one of the plurality of gate electrodes and the active region form a transistor;
- forming an opening in the mask layer to expose the one of the plurality of electrode lines and the well pickup region;
- etching portions of the plurality of gate electrode lines exposed through the opening;
- forming an inter-layer dielectric (ILD) over the plurality of gate electrode lines and the well pickup region;
- and
- forming a contact plug in the ILD and electrically coupled to the well pickup region.
8 more elements
A method comprising:
- blanket forming a mask layer over a semiconductor wafer, wherein the semiconductor wafer comprises:
- a plurality of gate electrode lines comprising dummy gate electrode lines and active gate electrode lines, wherein the plurality of gate electrode lines are parallel to each other and have a uniform pitch;
- a p-well region and an n-well region;
- and
- a p-well pickup region and an n-well pickup region directly over the p-well region and the n-well region, respectively;
- forming a first and a second opening in the mask layer, wherein the p-well pickup region and two of the plurality of gate electrode lines are exposed through the first opening, and wherein the n-well pickup region and additional two of the plurality of gate electrode lines are exposed through the second opening;
- etching portions of the plurality of gate electrode lines exposed through the first and the second openings;
- forming an inter-layer dielectric (ILD) over the plurality of gate electrode lines and the first and the second well pickup regions;
- and
- forming a first and a second contact plug in the ILD and electrically coupled to the first and the second well pickup regions, respectively.
7 more elements
Dependencies are inferred from the claim text.