Low on-resistance power transistor, power converter, and related method

A power converter, comprising:

• a first power transistor, comprising:
• a drain, a source, and a channel therebetween, wherein the channel is divided into a plurality of channels that contribute to an overall effective channel width of the first power transistor;
• a first top metal associated with one of the source and the drain;
• and
• a second top metal associated with the other of the source and the drain, wherein the second top metal includes at least a first portion that couples with a first group of the plurality of channels from a first direction, and at least a second portion that couples with a second group of the plurality of channels from a second direction.

A method for determining a layout topology of a power transistor, the method comprising:

• estimating a resistance (R) of a power transistor based at least in part on a calculation from an equation using a first width, the equation comprising:
• R
• =
• ap
• c
• 
• (
• 
• 2
• 
• aw
• +
• 1
• )
• (
• 
• 2
• 
• aw
• -
• 1
• )
• ,
• wherein
• a
• =
• p
• m
• p
• c
• ,
• pm is a resistivity of a metal layer of the power transistor, pc is a resistivity of a channel of the power transistor, and w is a width of a plurality of transistor stripes of the power transistor;
• estimating another resistance of a power transistor based at least in part on a calculation from the equation using a second width of a plurality of transistor stripes of the power transistor;
• and
• defining a layout topology of the power transistor using the resistance and the another resistance to determine a quantity and width of transistor stripes for a layout topology of the power transistor responsive to a comparison of the resistance and the another resistance.