Semiconductor Device Die with Integrated MOSFET and Low Forward Voltage Diode-Connected Enhancement Mode JFET and Method

A method of making a semiconductor device die with integrated MOSFET and diode-connected enhancement mode JFET (DCE-JFET) wherein:

• the integrated MOSFET-JFET semiconductor device die has a lower common semiconductor substrate region (CSSR) of type-1 conductivity;
• the MOSFET is located at the top of the CSSR and having:
• the CSSR as its MOSFET drain region;
• at least a MOSFET body region of type-2 conductivity, a MOSFET gate region and a MOSFET source region of type-1 conductivity located at the top of the drain region;
• and
• the DCE-JFET is located at the top of the CSSR and having:
• the CSSR as its DCE-JFET drain region;
• at least two DCE-JFET gate regions of type-2 conductivity stacked atop the drain region and laterally separated from each other along the major CSSR plane with a DCE-JFET gate spacing;
• and
• at least a DCE-JFET source region of type-1 conductivity stacked atop the CSSR between the DCE-JFET gate regions;
• wherein the DCE-JFET source region is shorted to the DCE-JFET gate regions,
• the method comprises:
• a) providing the CSSR, partitioning its major plane into a MOSFET zone and a DCE-JFET zone then fabricating a MOSFET gate region in the MOSFET zone;
• b) creating the MOSFET body region in the MOSFET zone and the DCE-JFET gate regions in the DCE-JFET zone;
• and
• c) creating the MOSFET source region in the MOSFET zone and the DCE-JFET source region in the DCE-JFET zone;
• and
• d) shorting the DCE-JFET source region to the DCE-JFET gate regions.