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US 2012/0058597 A1Published application
Fabrication method for thin-film field-effect transistors
AssigneeImperial Innovations Limited
InventorsThomas Anthopoulos, Donal Donat Conor Bradley, Jeremy Nicholas Smith
Life of this patent
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Abstract
A thin-film field-effect transistor is formed by forming a dielectric layer adjacent a gate, forming a source region and a drain region, and forming a semiconductor layer on the dielectric layer. The semiconductor layer is deposited by spray pyrolysis and comprises a material selected from a group comprising: oxides; oxide-based materials; mixed oxides; metallic type oxides; group I-IV, II-VI, III-VI, IV-VI, V-VI and VIII-VI binary chalcogenides; and group I-II-VI, II-II-VI, II-III-VI, II-VI-VI and V-II-VI ternary chalcogenides.
Claims15
1-31. (canceled)
32:
- A method of forming a thin-film field-effect transistor, the method comprising the steps of:
- forming a dielectric layer adjacent a gate;
- forming a source region and a drain region;
- and
- forming a semiconductor layer on the dielectric layer;
- wherein the semiconductor layer is deposited by spray pyrolysis and comprises a material selected from a group comprising:
- oxides;
- oxide-based materials;
- mixed oxides;
- metallic type oxides;
- group I-IV, II-VI, III-VI, IV-VI, V-VI and VIII-VI binary chalcogenides;
- and group I-II-VI, II-II-VI, II-III-VI, II-VI-VI and V-II-VI ternary chalcogenides.
9 more elements
33:
- A method of forming a thin-film field-effect transistor, the method comprising the steps of:
- preparing a substrate having a dielectric layer adjacent a gate;
- forming a source region and a drain region;
- and
- forming a semiconductor layer on the dielectric layer;
- wherein the semiconductor layer is deposited by spray pyrolysis and comprises a material selected from a group comprising:
- oxides other than titanium dioxide;
- oxide-based materials;
- mixed oxides;
- metallic type oxides;
- group I-IV, II-VI, III-VI, IV-VI, V-VI and VIII-VI binary chalcogenides;
- and group I-II-VI, II-II-VI, II-III-VI, II-VI-VI and V-II-VI ternary chalcogenides.
9 more elements
34:
- The method as claimed in claim 32, wherein the semiconductor layer is deposited using a precursor solution, the precursor solution being doped in order to incorporate dopant atoms in the semiconductor material once formed.
35:
- The method as claimed in claim 34, wherein the dopant atoms are selected from a group comprising:
- aluminum, indium, gallium, molybdenum, boron, nitrogen, and lithium.
36:
- The method as claimed in claim 32, wherein the spray pyrolysis is performed at a temperature in the range of 100° C. to 400° C.
37:
- The method as claimed in claim 32, wherein the semiconductor layer is formed of zinc oxide.
38:
- The method as claimed in claim 32, further comprising depositing the source and/or drain regions, and/or the gate, by spray pyrolysis.
39:
- The method as claimed in claim 38, wherein the source and/or drain regions, and/or the gate, deposited by spray pyrolysis, is/are formed of a conductive oxide.
40:
- The method as claimed in claim 39, wherein the conductive oxide comprises a doped metal oxide as one of indium doped tin oxide and aluminum doped zinc oxide.
41:
- The method as claimed in claim 32, wherein the gate is formed of a conductive polymer.
42:
- The method as claimed in claim 32, wherein the gate and/or substrate and/or source and drain regions are formed of flexible materials.
43:
- The method as claimed in claim 32, wherein the dielectric layer is formed of an organic/polymer material.
44:
- The method as claimed in claim 43, wherein the organic/polymer material is a perfluoropolymer, polystyrene, poly(methyl methacrylate), a crosslinkable monomer or polymer, a ferroelectric polymer, or a derivative or co-polymer of any of the above.
45:
- The method as claimed in claim 32, wherein the semiconductor layer is deposited before the dielectric layer, and wherein the gate is formed after the dielectric layer, and wherein a surface of the semiconductor layer is treated with plasma prior to the deposition of the dielectric layer.