Integrated circuit wafer dicing method

Abstract

An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits on a wafer substrate, forming a patterned protective layer on the integrated circuits, and etching through the wafer substrate to form a plurality of integrated circuit dies by using the patterned protective layer as a mask. The patterned protective layer is preferably a patterned photoresist layer. The step of forming the patterned protective layer includes covering the wafer substrate with a photoresist layer, exposing the photoresist layer by using a photomask, and developing the exposed photoresist layer to form the patterned protective layer. The etching process can be dry etching or wet etching.

Dependencies are inferred from the claim text.